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2 |
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moderate
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Proxies\__CG__\App\Entity\Entry {#1571
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Show voter details
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3 |
DENIED
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edit
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Proxies\__CG__\App\Entity\Entry {#1571
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Show voter details
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4 |
DENIED
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moderate
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Proxies\__CG__\App\Entity\Entry {#1571
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Show voter details
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5 |
DENIED
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ROLE_USER
|
null |
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Show voter details
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6 |
DENIED
|
moderate
|
App\Entity\EntryComment {#1696
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Show voter details
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7 |
DENIED
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edit
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App\Entity\EntryComment {#1696
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Show voter details
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8 |
DENIED
|
moderate
|
App\Entity\EntryComment {#1696
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+createdAt: DateTimeImmutable @1703464329 {#1698
date: 2023-12-25 01:32:09.0 +01:00
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…2
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+magazine: Proxies\__CG__\App\Entity\Magazine {#1572 …}
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+parent: Proxies\__CG__\App\Entity\EntryComment {#1650 …}
+root: Proxies\__CG__\App\Entity\EntryComment {#1679 …}
+body: "All even half-way relevant architectures but x86 and z/Architecture are RISC nowadays: ARM, Power, MIPS (The Chinese tried to revitalise it but they seem to be switching to RISC-V), Atmel AVR. Oh speaking of microcontrollers: Z80 (CISC) still lives though arguably it’s genetically an x86. And then of course RISC-V which most of all is an open standard, and a clean slate. Also, the first vector insn set that also runs on hardware that isn’t a supercomputer."
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date: 2023-12-26 01:28:58.0 +01:00
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"@Zeon@lemmy.world"
"@kittenzrulz123@lemmy.world"
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-id: 270893
-bodyTs: "'also':70,77 'architectur':7 'arguabl':45 'arm':15 'atmel':34 'avr':35 'chines':19 'cisc':41 'clean':68 'cours':54 'even':2 'first':72 'genet':48 'half':4 'half-way':3 'hardwar':80 'insn':74 'isn':82 'live':43 'microcontrol':39 'mip':17 'nowaday':14 'oh':36 'open':64 'power':16 'relev':6 'revitalis':22 'risc':13,32,56 'risc-v':31,55 'run':78 'seem':26 'set':75 'slate':69 'speak':37 'standard':65 'still':42 'supercomput':85 'switch':29 'though':44 'tri':20 'v':33,57 'vector':73 'way':5 'x86':9,50 'z/architecture':11 'z80':40"
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date: 2023-12-26 01:28:58.0 +01:00
}
+"title": 270893
} |
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