CMOS silicon logic can be chemically “printed” using photolithography and commercially available mercury lamps. From the wikipedia article, if I read between the lines those are good down to feature sizes of about 1 micron (1.0µM or 1000nm), limited of course by the accuracy of your wafer setups between processes and the printing of your lithography plates. this is the process used to produce the Intel 80486 which fit 1 million transistors on a chip. seems that laser lithography using KrF lasers can be good down to much smaller but your litho plates become the limiting factor.
so, conservatively- 1µm features would be attainable for a sort of “home brew” startup with little to no venture funding but the correct industrial knowledge. with more funding though i’d guess older laser lithography machines would be attainable on the used market and potentially usable down to 0.4µm or smaller.